Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips

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	Similar Articles Articles by Santanu Chattopadhyay Articles by K. Sudarsana Reddy

16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	Santanu Chattopadhyay, K. Sudarsana Reddy, "Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips," VLSI Design, International Conference on, pp. 341, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183160, author = {Santanu Chattopadhyay and K. Sudarsana Reddy}, title = {Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {341}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183160}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips SN - 1063-9667 SP EP A1 - Santanu Chattopadhyay, A1 - K. Sudarsana Reddy, PY - 2003 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Santanu Chattopadhyay, Indian Institute of Technology Guwahati

K. Sudarsana Reddy, Indian Institute of Technology Guwahati

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183160

We present a Genetic algorithm (GA) based approach to solve the problems of Test Scheduling and Test Access Mechanism partition for System on Chips. The approach provides highly optimal results comparable to the Integer Linear Programming formulation of similar problems within very small CPU times. The results of GA based approach are shown to be superior to the heuristic approaches proposed in the literature.

Citation:

Santanu Chattopadhyay, K. Sudarsana Reddy, "Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips," vlsid, pp.341, 16th International Conference on VLSI Design, 2003

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