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16th International Conference on VLSI Design
A Low-Voltage Low Power CMOS Companding Filter
New Delhi, India
January 04-January 08
ISBN: 0-7695-1868-0
J. Veerendra Kumar, Indian Institute of Technology Madras
K. Radhakrishna Rao, Indian Institute of Technology Madras
Cmos companding filters exploit compressed I-V characteristics of MOSFET and reduce voltage swings at internal nodes, thus allowing large dynamic range in low supply voltage environment. Companding filters replace gm-c filters in low voltage environment for higher dynamic range. Square-root domain filters and log-domain filters belong to this class of companding filters. The former uses quadratic law of MOSFET in strong inversion region. Low power, low voltage and high frequency building blocks are needed for improved performance filters in VLSI. In this paper, a current-mode Square-root domain filter with a novel current-mode geometric-mean and current squarer circuit, based on up-down MOS Translinear Loop is presented. The main advantages of the proposed circuits over others are low power, low voltage, less circuit complexity and less signal dependent errors without complex current injection. Further, it is operative at higher frequencies. Body effect is minimized due to up-down voltage translinear loop and isolation of the currents eliminates the redundancy, if the same current is used repetitively. These filters find their applications in current-controlled oscillators and in the design of low power low voltage current-mode video frequency filters.
Citation:
J. Veerendra Kumar, K. Radhakrishna Rao, "A Low-Voltage Low Power CMOS Companding Filter," vlsid, pp.309, 16th International Conference on VLSI Design, 2003
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