Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology

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VLSID
2003
16th International Conference on VLSI Design
Abstract - Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology

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	Similar Articles Articles by Koushik K. Das Articles by Richard B. Brown

16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	Koushik K. Das, Richard B. Brown, "Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology," VLSI Design, International Conference on, pp. 291, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183152, author = {Koushik K. Das and Richard B. Brown}, title = {Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {291}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183152}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology SN - 1063-9667 SP EP A1 - Koushik K. Das, A1 - Richard B. Brown, PY - 2003 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Koushik K. Das, University of Michigan

Richard B. Brown, University of Michigan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183152

As supply voltage is scaled to below 1 V, leakage power becomes significant in CMOS ICs. This paper proposes novel circuit techniques in PD-SOI technology to reduce standby power in the sub-1 V regime by over three orders of magnitude while maintaining circuit speed and with minimal overhead. Simulation results obtained using process parameters from an IBM 0.13 m PD-SOI technology show considerable improvement over previously proposed methods as supply voltage is scaled to 0.5 V. A new design algorithm for efficient implementation of these PD-SOI standby power reduction schemes is also described.

Citation:

Koushik K. Das, Richard B. Brown, "Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology," vlsid, pp.291, 16th International Conference on VLSI Design, 2003

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