Non-volatile memories (NVMs) are susceptible to special type of faults known as disturb faults. A class of these disturb faults are faults induced by high electric field stress known as program disturbs. In this paper we discuss the physical nature of the defects that are responsible for these faults in flash memories. We develop an electrical fault model for defects and simulate faulty cell behavior based on physical defect location (in gate oxide). We also evaluate the impact of these defects on cell performance. The modeling technique is flexible and applicable under different disturb conditions and defect characteristics.