A Memory Efficient 3-D DWT Architecture

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16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	B. Das, Swapna Banerjee, "A Memory Efficient 3-D DWT Architecture," VLSI Design, International Conference on, pp. 208, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183138, author = {B. Das and Swapna Banerjee}, title = {A Memory Efficient 3-D DWT Architecture}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {208}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183138}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A Memory Efficient 3-D DWT Architecture SN - 1063-9667 SP EP A1 - B. Das, A1 - Swapna Banerjee, PY - 2003 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

B. Das, Indian Institute of Technology

Swapna Banerjee, Indian Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183138

This paper proposes a memory efficient real-time 3-D DWT algorithm and its architectural implementation. As the running JD-DWT refreshes the wavelet coefficients with the arrival of every two new frames, the latency of the conventional 3D- DWT reduces by at least ¼ times. For realization of the transform canonical signed digit multiplier has been used. Parallelism being an added advantage for fast processing has been used with three pipelined stages in this architecture. For coefficient mapping, correlation between LPF and HPF in orthogonal Daubechies wavelet filter has been used. In this design the mem- ory requirement has been optimized to the order O(KN² + (K - 2) x N). The proposed architecture has been implemented on Xilinx FPGA devices at an operating frequency of 75MHz. This low complex architecture ensures 100% hardware utilization.

Citation:

B. Das, Swapna Banerjee, "A Memory Efficient 3-D DWT Architecture," vlsid, pp.208, 16th International Conference on VLSI Design, 2003

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