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16th International Conference on VLSI Design
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node
New Delhi, India
January 04-January 08
ISBN: 0-7695-1868-0
ASCII Text
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V. Menezes, C. B. Keshav, S. Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau, "Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node," VLSI Design, International Conference on, pp. 122, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183125,
author = {V. Menezes and C. B. Keshav and S. Gupta and M. Roopashree and S. Krishnan and A. Amerasekera and G. Palau},
title = {Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {122},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183125},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node
SN - 1063-9667
SP
EP
A1 - V. Menezes,
A1 - C. B. Keshav,
A1 - S. Gupta,
A1 - M. Roopashree,
A1 - S. Krishnan,
A1 - A. Amerasekera,
A1 - G. Palau,
PY - 2003
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
V. Menezes, Texas Instruments India
C. B. Keshav, Texas Instruments India
S. Gupta, STMicroelectronics India
M. Roopashree, Texas Instruments India
S. Krishnan, Texas Instruments Inc Dallas
A. Amerasekera, Texas Instruments Inc Dallas
G. Palau, Texas Instruments Inc Dallas
We describe the methodology and challenges in designing robust receiver and driver buffers in a sate-of-the-art sub-100nm CMOS technology. Issues addressed are the gate voltage limitations due to very thin gate oxides, channel hot carriers, process variability and design margins. The bi-directional buffer is 90 um x 114 um in size and has a maximum speed of 150 MHz with a 50 ohm termination.
Citation:
V. Menezes, C. B. Keshav, S. Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau, "Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node," vlsid, pp.122, 16th International Conference on VLSI Design, 2003
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