A New Approach to Analyze a Sub-micron CMOS Inverter

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	Similar Articles Articles by Manisha Pattanaik Articles by Swapna Banerjee

16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	Manisha Pattanaik, Swapna Banerjee, "A New Approach to Analyze a Sub-micron CMOS Inverter," VLSI Design, International Conference on, pp. 116, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183124, author = {Manisha Pattanaik and Swapna Banerjee}, title = {A New Approach to Analyze a Sub-micron CMOS Inverter}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {116}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183124}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - A New Approach to Analyze a Sub-micron CMOS Inverter SN - 1063-9667 SP EP A1 - Manisha Pattanaik, A1 - Swapna Banerjee, PY - 2003 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Manisha Pattanaik, Dept. of E & ECE, IIT

Swapna Banerjee, Dept. of E & ECE, IIT

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183124

An analytical model is proposed for submicron CMOS devices based on Thornber?s scaling law where the field dependent mobility and carrier velocity saturation are treated independently. Comparison of simulated results with the experimental results of I~V data for sub and deep sub micrometer MOSFETs down to 0.09-?m effective gate length demonstrates the accuracy of the model. A sub micron CMOS (0.2-?m technology) inverter is analyzed by using the proposed model. Results show that the calculated propagation delay and output voltage waveform are in good agreement with Spectre simulation results.

Citation:

Manisha Pattanaik, Swapna Banerjee, "A New Approach to Analyze a Sub-micron CMOS Inverter," vlsid, pp.116, 16th International Conference on VLSI Design, 2003

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