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16th International Conference on VLSI Design
Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy
New Delhi, India
January 04-January 08
ISBN: 0-7695-1868-0
ASCII Text
x 
 
Zhibin Dai, Dilip K. Banerji, "Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy," VLSI Design, International Conference on, pp. 85, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183119,
author = {Zhibin Dai and Dilip K. Banerji},
title = {Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {85},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183119},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy
SN - 1063-9667
SP
EP
A1 - Zhibin Dai,
A1 - Dilip K. Banerji,
PY - 2003
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Zhibin Dai, Visual Insights
Dilip K. Banerji, University of Guelph
Field Programmable Gate Arrays (FPGAs) have emerged as the key technology for rapidly implementing digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is their routing implementation, which is greatly affected by the routing architecture and routing resources. This paper explores the effective utilization of a routing hierarchy that is present in the currently available commercial FPGAs. A stochastic model is adopted to investigate the routability on symmetrical FPGAs containing a routing resource hierarchy. The performance of our model is compared to that of an FPGA without a routing hierarchy. Experimental methods are used to determine the switch consumption of various routing resources. Results show that integrating a routing resource hierarchy into FPGAs causes a design to consume fewer routing resources. Consequently, the speed of designs implemented in such FPGAs can be greatly improved.
Citation:
Zhibin Dai, Dilip K. Banerji, "Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy," vlsid, pp.85, 16th International Conference on VLSI Design, 2003
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