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16th International Conference on VLSI Design
Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
New Delhi, India
January 04-January 08
ISBN: 0-7695-1868-0
ASCII Text
x 
 
Rohit Pandey, Santanu Chattopadhyay, "Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"," VLSI Design, International Conference on, pp. 79, 16th International Conference on VLSI Design, 2003.
 
 
BibTex
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@article{ 10.1109/ICVD.2003.1183118,
author = {Rohit Pandey and Santanu Chattopadhyay},
title = {Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2003},
issn = {1063-9667},
pages = {79},
doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183118},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"
SN - 1063-9667
SP
EP
A1 - Rohit Pandey,
A1 - Santanu Chattopadhyay,
PY - 2003
KW - null
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Rohit Pandey, Indian Institute of Technology
Santanu Chattopadhyay, Indian Institute of Technology
In this paper we consider the problem of LookUp Table(LUT) based FPGA technology mapping for power minimization in combinational circuits. The problem has been previously proven to be NP-complete and here we present an efficient Genetic Algorithm solution for it. Considering that the connection switches posses large resistance and capacitance in LUT based FPGA, the fitness of the chromosome is selected based on its ability to reduce the transition probability on "visible" edges of mapped logic circuits by hiding the paths with high transition activity in the "invisible" edges. Meanwhile, the number of LUT is also kept small.
Citation:
Rohit Pandey, Santanu Chattopadhyay, "Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach"," vlsid, pp.79, 16th International Conference on VLSI Design, 2003
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