Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25?m CMOS

V
VLSID
2003
16th International Conference on VLSI Design
Abstract - Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25?m CMOS

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16th International Conference on VLSI Design

New Delhi, India

January 04-January 08

ISBN: 0-7695-1868-0

	ASCII Text	x
	Saikat Sarkar, Padmanava Sen, Arvind Raghava, Sudipto Chakarborty, Joy Laskar, "Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25?m CMOS," VLSI Design, International Conference on, pp. 42, 16th International Conference on VLSI Design, 2003.

	BibTex	x
	@article{ 10.1109/ICVD.2003.1183113, author = {Saikat Sarkar and Padmanava Sen and Arvind Raghava and Sudipto Chakarborty and Joy Laskar}, title = {Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25?m CMOS}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2003}, issn = {1063-9667}, pages = {42}, doi = {http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183113}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25?m CMOS SN - 1063-9667 SP EP A1 - Saikat Sarkar, A1 - Padmanava Sen, A1 - Arvind Raghava, A1 - Sudipto Chakarborty, A1 - Joy Laskar, PY - 2003 KW - null VL - 0 JA - VLSI Design, International Conference on ER -

Saikat Sarkar, Indian Institute of Technology

Padmanava Sen, Indian Institute of Technology

Arvind Raghava, Georgia Institute of Technology

Sudipto Chakarborty, Georgia Institute of Technology

Joy Laskar, Georgia Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ICVD.2003.1183113

This paper presents the design of a 2.4 GHz RF transceiver front-end chipset in 0.25 ?m CMOS technology. The designed chipset include a fully monolithic receiver front end consisting of LNA, mixer and two variations of power amplifiers (PA), one for high output power and efficiency, and the other for good linearity. The integrated receiver provides simulated voltage gain of 22.7 dB, NF of 6.6 dB, IIP3 of -15.5 dBm, and consumes 21 mW power from a 1.5 volt power supply. The high-efficiency versions utilize class F/ inverse class F matching to achieve power added efficiency (PAE) of over 50% with an output power of upto 350mW. The linear PA utilizes differential class B push pull architecture and provides an IM3 less than -35 dB with a 22.5 dBm output power and power added efficiency (PAE) of 20%. The circuits are under fabrication in National Semiconductor?s 0.25 ?m CMOS facility and the measurement results will be presented in the final version.

Citation:

Saikat Sarkar, Padmanava Sen, Arvind Raghava, Sudipto Chakarborty, Joy Laskar, "Development of 2.4 GHz RF Transceiver Front-end Chipset in 0.25?m CMOS," vlsid, pp.42, 16th International Conference on VLSI Design, 2003

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