Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting

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	Similar Articles Articles by Sagar Sabade Articles by Hank Walker

ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Sagar Sabade, Hank Walker, "Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting," VLSI Design, International Conference on, pp. 755, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.995024, author = {Sagar Sabade and Hank Walker}, title = {Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {755}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.995024}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting SN - 0-7695-1441-3 SP EP A1 - Sagar Sabade, A1 - Hank Walker, PY - 2002 VL - 0 JA - VLSI Design, International Conference on ER -

Sagar Sabade, Texas A&M University

Hank Walker, Texas A&M University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.995024

The quiescent current testing (IDDQ testing) for CMOS ICs provides several advantages over other testing methods. However, the future of IDDQ testing is threatened by increased sub-threshold leakage current for new technologies. The conventional pass/fail limit setting methodology cannot survive in its present form. In this paper we evaluate two statistical outlier rejection methods - the Chauvenet's criterion and the Tukey test - for their applicability to IDDQ testing. They are compared with the static-threshold method. The results of the analysis of application of these methods to the SEMATECH data1 are presented.

Citation:

Sagar Sabade, Hank Walker, "Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting," vlsid, pp.755, ASP-DAC/VLSI Design 2002, 2002

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