Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST

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	Similar Articles Articles by Nadir Z. Basturkmen Articles by Sudhakar M. Reddy Articles by Janusz Rajski

ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski, "Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST," VLSI Design, International Conference on, pp. 604, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.995003, author = {Nadir Z. Basturkmen and Sudhakar M. Reddy and Janusz Rajski}, title = {Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {604}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.995003}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST SN - 0-7695-1441-3 SP EP A1 - Nadir Z. Basturkmen, A1 - Sudhakar M. Reddy, A1 - Janusz Rajski, PY - 2002 VL - 0 JA - VLSI Design, International Conference on ER -

Nadir Z. Basturkmen, University of Iowa

Sudhakar M. Reddy, University of Iowa

Janusz Rajski, Mentor Graphics Corporation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.995003

New test point selection algorithms to improve test point insertion quality and performance of multi-phase test point insertion scheme, while reducing the memory requirement of the analyses are proposed. A new memory efficient probabilistic fault simulation method, which also handles the reconvergences to a limited extent for increased accuracy, is introduced. Synergistic control point insertion is targeted for higher test point insertion quality. Experiments conducted on various large industrial circuits demonstrate the effectiveness of the new algorithms.

Citation:

Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski, "Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST," vlsid, pp.604, ASP-DAC/VLSI Design 2002, 2002

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