Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Subhayu Basu, Debdeep Mukhopadhay, Dipanwita Roychoudhury, Indranil Sengupta, Sudipta Bhawmik, "Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch," VLSI Design, International Conference on, pp. 598, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.995001, author = {Subhayu Basu and Debdeep Mukhopadhay and Dipanwita Roychoudhury and Indranil Sengupta and Sudipta Bhawmik}, title = {Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {598}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.995001}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch SN - 0-7695-1441-3 SP EP A1 - Subhayu Basu, A1 - Debdeep Mukhopadhay, A1 - Dipanwita Roychoudhury, A1 - Indranil Sengupta, A1 - Sudipta Bhawmik, PY - 2002 KW - Test Access Mechanism KW - Data acyclic graph KW - Test patterns KW - Test time KW - System-on-Chip VL - 0 JA - VLSI Design, International Conference on ER -

Subhayu Basu, Princeton University

Debdeep Mukhopadhay, Indian Institute of Technology at Kharagpur

Dipanwita Roychoudhury, Indian Institute of Technology at Kharagpur

Indranil Sengupta, Indian Institute of Technology at Kharagpur

Sudipta Bhawmik, Agere systems

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.995001

In the present paper a new algorithm for reformatting the test vector of System On Chip (SOC) with Test Access Mechanism (TAM) has been proposed. Exhaustive experimentation has been done by employing random reformatted test vectors to a variety of SOCs, constructed with the ISCAS sequential benchmark circuits. For a limited number of input pins, which has been provided for testing the SOC, the proposed algorithm reduces drastically the test-time as well as the hardware.

Index Terms:

Test Access Mechanism, Data acyclic graph, Test patterns, Test time, System-on-Chip

Citation:

Subhayu Basu, Debdeep Mukhopadhay, Dipanwita Roychoudhury, Indranil Sengupta, Sudipta Bhawmik, "Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch," vlsid, pp.598, ASP-DAC/VLSI Design 2002, 2002

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