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ASP-DAC/VLSI Design 2002
Constraint Driven Pin Mapping for Concurrent SOC Testing
Bangalore, India
January 07-January 11
ISBN: 0-7695-1441-3
ASCII Text
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Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, "Constraint Driven Pin Mapping for Concurrent SOC Testing," VLSI Design, International Conference on, pp. 511, ASP-DAC/VLSI Design 2002, 2002.
 
 
BibTex
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@article{ 10.1109/ASPDAC.2002.994971,
author = {Yu Huang and Sudhakar M. Reddy and Nilanjan Mukherjee and Chien-Chung Tsai and Omer Samman and Yahya Zaidan and Yanping Zhang and Wu-Tung Cheng},
title = {Constraint Driven Pin Mapping for Concurrent SOC Testing},
journal ={VLSI Design, International Conference on},
volume = {0},
year = {2002},
isbn = {0-7695-1441-3},
pages = {511},
doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994971},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Design, International Conference on
TI - Constraint Driven Pin Mapping for Concurrent SOC Testing
SN - 0-7695-1441-3
SP
EP
A1 - Yu Huang,
A1 - Sudhakar M. Reddy,
A1 - Nilanjan Mukherjee,
A1 - Chien-Chung Tsai,
A1 - Omer Samman,
A1 - Yahya Zaidan,
A1 - Yanping Zhang,
A1 - Wu-Tung Cheng,
PY - 2002
VL - 0
JA - VLSI Design, International Conference on
ER -
 
Yu Huang, University of Iowa
Sudhakar M. Reddy, University of Iowa
Nilanjan Mukherjee, Mentor Graphics Corporation
Chien-Chung Tsai, Mentor Graphics Corporation
Omer Samman, Mentor Graphics Corporation
Yahya Zaidan, Mentor Graphics Corporation
Yanping Zhang, Mentor Graphics Corporation
Wu-Tung Cheng, Mentor Graphics Corporation
A solution for mapping core I/O pins to System-On-a-Chip (SOC) I/O pins in order to achieve cost-efficient concurrent test for core-based designs is presented in this paper. The problem of pin mapping is first formulated as two well-known NP-complete problems. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total number of SOC pins needed and satisfying the test constraints specified by core integrators. Experimental results demonstrate the efficiency of the proposed method.
Citation:
Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, "Constraint Driven Pin Mapping for Concurrent SOC Testing," vlsid, pp.511, ASP-DAC/VLSI Design 2002, 2002
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