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ASP-DAC/VLSI Design 2002
A Novel Method to Improve the Test Efficiency of VLSI Tests
Bangalore, India
January 07-January 11
ISBN: 0-7695-1441-3
Hailong Cui, University of Nebraska-Lincoln
Sharad C. Seth, University of Nebraska-Lincoln
Shashank K. Mehta, Indian Institute of Technology
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas.
Citation:
Hailong Cui, Sharad C. Seth, Shashank K. Mehta, "A Novel Method to Improve the Test Efficiency of VLSI Tests," vlsid, pp.499, ASP-DAC/VLSI Design 2002, 2002
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