Probabilistic Analysis of Rectilinear Steiner Trees

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Probabilistic Analysis of Rectilinear Steiner Trees

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Chunhong Chen, "Probabilistic Analysis of Rectilinear Steiner Trees," VLSI Design, International Conference on, pp. 484, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994967, author = {Chunhong Chen}, title = {Probabilistic Analysis of Rectilinear Steiner Trees}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {484}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994967}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Probabilistic Analysis of Rectilinear Steiner Trees SN - 0-7695-1441-3 SP EP A1 - Chunhong Chen, PY - 2002 VL - 0 JA - VLSI Design, International Conference on ER -

Chunhong Chen, University of Windsor

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994967

Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design.We present a probabilistic analysis method for constructing rectilinear Steiner trees.The best solution under statistical sense is obtained for any given set of N points.Experiments show that our results are better than those by the previous technique or very close to the optima.

Citation:

Chunhong Chen, "Probabilistic Analysis of Rectilinear Steiner Trees," vlsid, pp.484, ASP-DAC/VLSI Design 2002, 2002

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