Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropriate circuit partioning, transistor sizing, choice of a suitable Sense Amplifier, a good resetting technique and judicial use of dual Vth transistors we have achieved a high speed memory without dissipating too much power. The Introduction gives the specifications of the memory that was our design target. In Section II, we describe the key techniques. Finally, we present the implementation on a testchip, and silicon measured results, which (we believe) is the best in class of embedded SRAM compliers available from various vendors in the world at the time of writing this paper. Also this architecture has achieved yields well over 95% in 0.18u technology.