Net Clustering Based Macrocell Placement

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Net Clustering Based Macrocell Placement

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	Similar Articles Articles by Stelian Alupoaei Articles by Srinivas Katkoori

ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Stelian Alupoaei, Srinivas Katkoori, "Net Clustering Based Macrocell Placement," VLSI Design, International Conference on, pp. 399, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994954, author = {Stelian Alupoaei and Srinivas Katkoori}, title = {Net Clustering Based Macrocell Placement}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {399}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994954}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Net Clustering Based Macrocell Placement SN - 0-7695-1441-3 SP EP A1 - Stelian Alupoaei, A1 - Srinivas Katkoori, PY - 2002 KW - Macrocell placement KW - force-directed placement KW - net clustering KW - net placement KW - net prioritization KW - iterative improvement VL - 0 JA - VLSI Design, International Conference on ER -

Stelian Alupoaei, University of South Florida

Srinivas Katkoori, University of South Florida

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994954

Given an RTL (Register-Transfer-Level) netlist, a net dependency graph with weighted edges is built. Each node in the graph represents a net and an edge exists between two nodes if the two nets represented by the nodes share one or more macrocells. Clusters of nets are then formed by clique partitioning. A net cluster level floorplan is derived by simulated annealing to define the regions where the nets in each cluster must be routed. The macrocell placement is formulated as a force-directed problem where the terminals of a net are free to move under the influence of forces in the quest for optimal length of the net. A new type of rejection force is introduced in order to obtain a feasible placement. In comparison with the placements generated by CADENCE Silicon Ensemble, we obtained an average total wire length reduction of 22.8% and an average longest wire length reduction of 33% with an average area penalty of only 1.1%.

Index Terms:

Macrocell placement, force-directed placement, net clustering, net placement, net prioritization, iterative improvement

Citation:

Stelian Alupoaei, Srinivas Katkoori, "Net Clustering Based Macrocell Placement," vlsid, pp.399, ASP-DAC/VLSI Design 2002, 2002

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