Interconnect with an insufficient width may be subject to electromigration and eventually cause the failure of the circuit at any time during its lifetime. This problem has gotten worse over the last couple of years due to the ongoing reduction of circuit feature sizes. For this reason, it is becoming crucial to address the problems of current densities and electromigration during layout generation. Here we present two new methodologies capable of routing analog multi-terminal signal nets with current-driven wire widths. Our first approach computes a Steiner tree layout satisfying all specified current constraints before performing a DRC- and current-correct point-to-point detailed routing. The second methodology is based on a terminal tree which defines a detailed terminal-to-terminal routing sequence. We also discuss successful applications of both methodologies in commercial analog circuits.