Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches

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	Similar Articles Articles by Maryam Shojaei Baghini Articles by Madhav P. Desai

ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Maryam Shojaei Baghini, Madhav P. Desai, "Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches," VLSI Design, International Conference on, pp. 317, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994941, author = {Maryam Shojaei Baghini and Madhav P. Desai}, title = {Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {317}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994941}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches SN - 0-7695-1441-3 SP EP A1 - Maryam Shojaei Baghini, A1 - Madhav P. Desai, PY - 2002 KW - Metastability KW - Technology Scaling KW - CMOS latches VL - 0 JA - VLSI Design, International Conference on ER -

Maryam Shojaei Baghini, MicroElectronics Group

Madhav P. Desai, MicroElectronics Group

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994941

In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are Tm and Tw. Tm is the exponential time constant of the rate of decay of metastability and Tw is effective size of metastability window at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate simulator for enough accuracy. Our simulations indicate that Tm scales better than the technology scale factor. Tw also scales down but its factor cannot be well estimated as that of Tm. This is because Tw is a complex function of signal and clock edge rate and logic threshold level.

Index Terms:

Metastability, Technology Scaling, CMOS latches

Citation:

Maryam Shojaei Baghini, Madhav P. Desai, "Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches," vlsid, pp.317, ASP-DAC/VLSI Design 2002, 2002

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