Architecture Implementation Using the Machine Description Language LISA

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr, "Architecture Implementation Using the Machine Description Language LISA," VLSI Design, International Conference on, pp. 239, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994928, author = {Oliver Schliebusch and Andreas Hoffmann and Achim Nohl and Gunnar Braun and Heinrich Meyr}, title = {Architecture Implementation Using the Machine Description Language LISA}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {239}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994928}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Architecture Implementation Using the Machine Description Language LISA SN - 0-7695-1441-3 SP EP A1 - Oliver Schliebusch, A1 - Andreas Hoffmann, A1 - Achim Nohl, A1 - Gunnar Braun, A1 - Heinrich Meyr, PY - 2002 KW - ASIP KW - Exploration KW - Implementation KW - Design KW - Synthesis KW - VHDL KW - Verilog KW - SystemC KW - LISA VL - 0 JA - VLSI Design, International Conference on ER -

Oliver Schliebusch, University of Technology Aachen

Andreas Hoffmann, University of Technology Aachen

Achim Nohl, University of Technology Aachen

Gunnar Braun, University of Technology Aachen

Heinrich Meyr, University of Technology Aachen

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994928

The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design implementation. The LISA processor design platform LPDP based on machine descriptions in the LISA language provides one common environment for these design phases. Required software tools for architecture exploration and application development can be generated from one sole specification. This paper focuses on the implementation phase and the generation of synthesizable HDL code from a LISA model. The derivation of the architectural structure, decoder and even approaches for the implementation of the data path are presented. Moreover, the synthesis results of a generated and a handwritten implementation of a low-power DVB-T post processing unit are compared.

Index Terms:

ASIP, Exploration, Implementation, Design, Synthesis, VHDL, Verilog, SystemC, LISA

Citation:

Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr, "Architecture Implementation Using the Machine Description Language LISA," vlsid, pp.239, ASP-DAC/VLSI Design 2002, 2002

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