Predictive delay analysis is presented for a representative CMOS inverter with submicron device size using PREDICTMOS MOSFET model. As against SPICE, which adopts a time consuming numerical approach and relies more on empirical fitting of parameters for short channel devices, the predictive MOSFET model used is relatively simple and can be related to process and layout data with potential of estimation of the performance of a scaled design. The submicron CMOS inverter delay estimation under various loading and operative conditions have been compared against two benchmarks (a) Computer aided simulation with SPICE level 3 and (b) The analytical results of the Alpha Power Law based model. It is concluded that the PREDICTMOS model is potentially promising as a predictive analytic tool for submicron level design with transparency of device or circuit physics and an acceptable level of accuracy.