Minimizing Energy Consumption for High-Performance Processing

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Minimizing Energy Consumption for High-Performance Processing

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti, "Minimizing Energy Consumption for High-Performance Processing," VLSI Design, International Conference on, pp. 199, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994919, author = {Eric F. Weglarz and Kewal K. Saluja and Mikko H. Lipasti}, title = {Minimizing Energy Consumption for High-Performance Processing}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {199}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994919}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Minimizing Energy Consumption for High-Performance Processing SN - 0-7695-1441-3 SP EP A1 - Eric F. Weglarz, A1 - Kewal K. Saluja, A1 - Mikko H. Lipasti, PY - 2002 KW - low power KW - parallel processing KW - energy savings KW - MPEG-2 KW - cache size KW - BTB size KW - voltage reduction KW - frequency reduction VL - 0 JA - VLSI Design, International Conference on ER -

Eric F. Weglarz, University of Wisconsin - Madison

Kewal K. Saluja, University of Wisconsin - Madison

Mikko H. Lipasti, University of Wisconsin - Madison

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994919

Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowered voltage and frequency to perform a similar amount of work in less time and lower power than a uniprocessor. The paper also studies the effect of reducing cache and Branch Target Buffer (BTB) sizes for further reducing power consumption while still providing adequate performance. The best configuration requiring four processors reduced energy by 56%. Reducing cache and BTB provided a further 16\% savings in energy while still finishing the workload in the same amount of time as the uniprocessor.

Index Terms:

low power, parallel processing, energy savings, MPEG-2, cache size, BTB size, voltage reduction, frequency reduction

Citation:

Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti, "Minimizing Energy Consumption for High-Performance Processing," vlsid, pp.199, ASP-DAC/VLSI Design 2002, 2002

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