Switching activity estimation is an important step in power estimation of digital VLSI circuits. While simulation yields accurate results, it is time consuming. In this paper, we propose a new technique based on Petri nets for real-delay switching activity estimation that yields the same accuracy as simulation, but is significantly faster in computation. We introduce a new type of Petri net called Hierarchical Colored Hardware Petri Net (HCHP-Net). The gate-level circuit is first transformed into a directed acyclic graph called, GSDAG, in which both the gates as well as the signals correspond to the nodes in the graph. The GSDAG is then mapped onto a corresponding HCHP-Net which is then simulated using a Petri net simulator. Experimental results for ISCAS '85 circuits are presented. The method replicates exactly the switching activity results for real-delay models produced by HSPICE and PowerMill. However, the per-pattern simulation time is about 51 times faster than the Synopsys PowerMill and 8900 times faster than the Avanti HSPICE.