Register Transfer Operation Analysis during Data Path Verification

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Register Transfer Operation Analysis during Data Path Verification

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	D. Sarkar, "Register Transfer Operation Analysis during Data Path Verification," VLSI Design, International Conference on, pp. 172, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994914, author = {D. Sarkar}, title = {Register Transfer Operation Analysis during Data Path Verification}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {172}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994914}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Register Transfer Operation Analysis during Data Path Verification SN - 0-7695-1441-3 SP EP A1 - D. Sarkar, PY - 2002 KW - Sequential Circuit Verification KW - Control Part - Data Path KW - Data Path Verification KW - RTL Behaviours VL - 0 JA - VLSI Design, International Conference on ER -

D. Sarkar, Indian Institute of Technology at Kharagpur

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994914

A control part - data path partition based sequential circuit verification scheme aimed at avoiding state explosion comprises two major modules namely, a data path verifier and a control part verifier. The functional specifications of these modules have been identified. Of the two broad tasks involved in data path verification, namely status condition analysis and register transfer operation analysis, a method for the second task along with its termination, soundness and completeness have been treated rigorously. Its performance on some data path architectures has been reported.

Index Terms:

Sequential Circuit Verification, Control Part - Data Path, Data Path Verification, RTL Behaviours

Citation:

D. Sarkar, "Register Transfer Operation Analysis during Data Path Verification," vlsid, pp.172, ASP-DAC/VLSI Design 2002, 2002

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