Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models

V
VLSID
2002
ASP-DAC/VLSI Design 2002
Abstract - Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models

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ASP-DAC/VLSI Design 2002

Bangalore, India

January 07-January 11

ISBN: 0-7695-1441-3

	ASCII Text	x
	Makoto Nagata, Youichi Nishimori, Takashi Morie, Atsushi Iwata, Yoshitaka Murasaka, "Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models," VLSI Design, International Conference on, pp. 71, ASP-DAC/VLSI Design 2002, 2002.

	BibTex	x
	@article{ 10.1109/ASPDAC.2002.994888, author = {Makoto Nagata and Youichi Nishimori and Takashi Morie and Atsushi Iwata and Yoshitaka Murasaka}, title = {Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models}, journal ={VLSI Design, International Conference on}, volume = {0}, year = {2002}, isbn = {0-7695-1441-3}, pages = {71}, doi = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994888}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Design, International Conference on TI - Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models SN - 0-7695-1441-3 SP EP A1 - Makoto Nagata, A1 - Youichi Nishimori, A1 - Takashi Morie, A1 - Atsushi Iwata, A1 - Yoshitaka Murasaka, PY - 2002 VL - 0 JA - VLSI Design, International Conference on ER -

Makoto Nagata, Hiroshima University

Youichi Nishimori, Hiroshima University

Takashi Morie, Hiroshima University

Atsushi Iwata, Hiroshima University

Yoshitaka Murasaka, A-R-Tec Corp.

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2002.994888

This paper presents a substrate noise analysis methodology that employs chip-level substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with a time-series divided parasitic capacitance model for time-domain power-supply current estimation.System-level simulation models generated accordingly to the methodology provide reliable substrate noise waveforms.Simulated waveforms for practical digital circuits on a 0.6-?m CMOS 4.5-mm square chip are well consistent with measurements with a 100-ps 100-?V resolution.Peak-to-peak substrate noise amplitudes for reduced-substrate noise as well as conventional designs show roughly the error of 10%compared with the measurements.

Citation:

Makoto Nagata, Youichi Nishimori, Takashi Morie, Atsushi Iwata, Yoshitaka Murasaka, "Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models," vlsid, pp.71, ASP-DAC/VLSI Design 2002, 2002

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