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35th Annual Simulation Symposium
Approximate Simulation of Distributed-Memory Multithreaded Multiprocessors
San Diego, California
April 14-April 18
ISBN: 0-7695-1552-5
W.M. Zuberek, Memorial University of Newfoundland
The performance of modern computer systems is increasingly limited by long latencies of accesses to their memory systems. Instruction-level multithreading is a technique to tolerate long latencies of memory accesses by switching from one instruction thread to another. The paper shows that the simulation-based performance evaluation of distributed-memory multithreaded multiprocessor systems can be significantly simplified by using approximate models, composed of only a few processors, but with some parameters adjusted to represent the behavior of the original system.
Index Terms:
distributed-memory multiprocessors, block multithreading, timed Petri nets, discrete-event simulation, performance analysis, approximate models
Citation:
W.M. Zuberek, "Approximate Simulation of Distributed-Memory Multithreaded Multiprocessors," ss, pp.0107, 35th Annual Simulation Symposium, 2002
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