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33rd Annual Simulation Symposium
Using the DEVS Paradigm to Implement a Simulated Processor
Washington, D.C.
April 16-April 22
ISBN: 0-7695-0598-8
Sergio Daicz, Universidad de Buenos Aires Pabell?n I
Alejandro Tróccoli, Universidad de Buenos Aires Pabell?n I
Sergio Zlotnik, Universidad de Buenos Aires Pabell?n I
Gabriel Wainer, Universidad de Buenos Aires Pabell?n I
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of the design, allowing the definition of individual components that can be lately integrated into a modeling hierarchy. The tool is designed for the use in Computer Architecture and Organization courses. Its goal is allowing the students to acquire some practice in the design and implementation of hardware components by using simulation.
Index Terms:
Simulation methods: Discrete-event simulation. Modeling methodology: DEVS models, Cell-DEVS models. Applications: traffic models
Citation:
Sergio Daicz, Alejandro Tróccoli, Sergio Zlotnik, Gabriel Wainer, "Using the DEVS Paradigm to Implement a Simulated Processor," ss, pp.58, 33rd Annual Simulation Symposium, 2000
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