Kwang II Park, Department of Electrical and Electronic Engineering Korea Advanced Institute of Science and Technology
Jun Sung Kim, Department of Electrical and Electronic Engineering Korea Advanced Institute of Science and Technology
Heung Bum Kim, Department of Electrical and Electronic Engineering Korea Advanced Institute of Science and Technology
Jong Hyuk Choi, Department of Electrical and Electronic Engineering Korea Advanced Institute of Science and Technology
Kyu Ho Park, Department of Electrical and Electronic Engineering Korea Advanced Institute of Science and Technology
The performance and efficiency of event-driven simulations, such as VHDL and Verilog simulation, depend on the number of events that occur during the simulation. In this paper, we classify events into two categories, sensitive events and insensitive events}, according to the necessity of simulations, and implement the optimization methodology that eliminates unnecessary simulations caused by the insensitive events. Five experiments show that optimized VHDL programs run much faster than the original ones.
Citation:
Kwang II Park, Jun Sung Kim, Heung Bum Kim, Jong Hyuk Choi, Kyu Ho Park, "The Acceleration of VHDL Simulation by Classifying Events," ss, pp.177, 30th Annual Simulation Symposium (SS '97), 1997