Digital logic and fault simulation of large VLSI circuits is one of the most compute-intensive tasks in digital analysis. This paper describes a special purpose time driven array processor for digital logic simulation. The new architecture uses a massively parallel processing element (PE) array in a SIMD architecture. Compiled event-driven technology and nominal transport delay timing analysis are used. A circuit to be simulated is levelized according to the delay time order at the preprocessing stage and the levelized circuit is mapped into a massively parallel PE array. Circuit comparisons show that the speedup of the new architecture is up to 8 times faster than the MARS accelerator and it can be higher for increased circuit size; while the hardware cost remains low.