Several algebraic operations can be efficiently implemented by arrays of functional units such as systolic arrays. Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to a small set of computational problems due to their lack of flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative systolic architectures can be explored and powerful tools are needed to model and evaluate them. Well-Known rewriting-logic environments such as ELAN and Maude can be used to specify, simulate and even synthesize complex application specific digital systems. In this paper we propose the use of rewriting-logic to model and evaluate reconfigurable systolic architectures which are applied to the efficient treatment of algebraic operations such as matrix multiplication and the FFT.