NeuroSymbolic Processing: Non-Monotonic Operators and Their FPGA Implementation

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VI Brazilian Symposium on Neural Networks (SBRN'00)

Rio de Janeiro, Brazil

January 22-January 25

ISBN: 0-7695-0856-1

	ASCII Text	x
	E. Burattini, M. de Gregorio, G. Tamburrini, "NeuroSymbolic Processing: Non-Monotonic Operators and Their FPGA Implementation," Neural Networks, Brazilian Symposium on, pp. 2, VI Brazilian Symposium on Neural Networks (SBRN'00), 2000.

	BibTex	x
	@article{ 10.1109/SBRN.2000.889705, author = {E. Burattini and M. de Gregorio and G. Tamburrini}, title = {NeuroSymbolic Processing: Non-Monotonic Operators and Their FPGA Implementation}, journal ={Neural Networks, Brazilian Symposium on}, volume = {0}, year = {2000}, issn = {1522-4899}, pages = {2}, doi = {http://doi.ieeecomputersociety.org/10.1109/SBRN.2000.889705}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Neural Networks, Brazilian Symposium on TI - NeuroSymbolic Processing: Non-Monotonic Operators and Their FPGA Implementation SN - 1522-4899 SP EP A1 - E. Burattini, A1 - M. de Gregorio, A1 - G. Tamburrini, PY - 2000 VL - 0 JA - Neural Networks, Brazilian Symposium on ER -

E. Burattini, C.N.R.

M. de Gregorio, C.N.R.

G. Tamburrini, Universit? di Pisa

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/SBRN.2000.889705

Recalling the insights of McCulloch and Pitts [4], von Neumann [9] and Minsky [5] we introduce some non-monotonic operators implemented by means of new electronic devices (FPGA) for a NeuroSymbolic Processor (NSP). Some nets performing logical and arithmetic functions are also presented.

Citation:

E. Burattini, M. de Gregorio, G. Tamburrini, "NeuroSymbolic Processing: Non-Monotonic Operators and Their FPGA Implementation," sbrn, pp.2, VI Brazilian Symposium on Neural Networks (SBRN'00), 2000

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