Fast Parallel FFT on a Reconfigurable Computation Platform

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	Similar Articles Articles by Amir H. Kamalizad Articles by Chengzhi Pan Articles by Nader Bagherzadeh

15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'03)

S?o Paulo, SP - Brazil

November 10-November 12

ISBN: 0-7695-2046-4

	ASCII Text	x
	Amir H. Kamalizad, Chengzhi Pan, Nader Bagherzadeh, "Fast Parallel FFT on a Reconfigurable Computation Platform," Computer Architecture and High Performance Computing, Symposium on, pp. 254, 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'03), 2003.

	BibTex	x
	@article{ 10.1109/CAHPC.2003.1250345, author = {Amir H. Kamalizad and Chengzhi Pan and Nader Bagherzadeh}, title = {Fast Parallel FFT on a Reconfigurable Computation Platform}, journal ={Computer Architecture and High Performance Computing, Symposium on}, volume = {0}, year = {2003}, isbn = {0-7695-2046-4}, pages = {254}, doi = {http://doi.ieeecomputersociety.org/10.1109/CAHPC.2003.1250345}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Computer Architecture and High Performance Computing, Symposium on TI - Fast Parallel FFT on a Reconfigurable Computation Platform SN - 0-7695-2046-4 SP EP A1 - Amir H. Kamalizad, A1 - Chengzhi Pan, A1 - Nader Bagherzadeh, PY - 2003 KW - null VL - 0 JA - Computer Architecture and High Performance Computing, Symposium on ER -

Amir H. Kamalizad, University of California at Irvine

Chengzhi Pan, University of California at Irvine

Nader Bagherzadeh, University of California at Irvine

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/CAHPC.2003.1250345

This paper presents implementation of a very fast parallel complex FFT on M2, the second generation of MorphoSys Reconfigurable computation platform, which is targeting on streamed applications such as multimedia and DSP. The proposed mapping comprises fast presorting, cascaded radix-2 stages, and post-reordering. Data and twiddle factors are 16-bit real and 16-bit imaginary in 2?s complement format and scaling is performed to avoid overflow. The mapping is tested on our cycle-accurate simulator, "Mulate", and the performance is encouragingly better than other architectures such as Imagine and VIRAM. Moreover, the performance is scalable according to FFT sizes. Since there is no functionality specifically tailored to FFT, the results demonstrate the capability of MorphoSys architecture to extract parallelism from streamed applications. Further rationales are given based on the concepts of scalar operand networks and memory hierarchy.

Citation:

Amir H. Kamalizad, Chengzhi Pan, Nader Bagherzadeh, "Fast Parallel FFT on a Reconfigurable Computation Platform," sbac-pad, pp.254, 15th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'03), 2003

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