This paper presents T&D-Bench, an integrated suite of tools for modeling and simulating state-of-the-art processors, which is composed of two main parts. SimPL is an object-oriented methodology for modeling the behavior of an instruction set, with precise information on the timing of basic instruction steps. The methodology is general and allows easy modeling of various architecture types. The second part of the suite is CSPSim, an open set of visualization tools that communicate with any number of SimPL models based on a client-server architecture. T&D-Bench gathers the main advantages of teaching environments, with a rich user interface, and design environments, with resources for modeling any complex processor architectures.