Proposed real-time system implementations combine reconfigurable hardware (for speed-up) with processor-memory architectures. Such hardware can execute many functions in parallel, leading to a limited parallel system where a single software process can execute on the processor at any time, in parallel with a number of functions implemented on the reconfigurable hardware. This approach is not amenable to conventional fixed priority timing analysis, as fundamental assumptions are compromised, namely that of a critical instant. This paper describes generalised fixed priority timing analysis for limited parallel systems, illustrated by an example system utilising Field Programmable Gate Arrays as the reconfigurable hardware resource.