In CMOS circuits, power consumption is proportional to the product of the frequency and the square of the supply voltage. Hence, any reductions in the operating frequency of the processor and its supply voltage can lead to significant savings in energy consumption (and heat dissipation) but cause longer execution times. The application of dynamic voltage scaling (DVS) techniques to real-time systems must therefore attempt to minimize energy while guaranteeing the schedulability of the real-time tasks. In this paper, we study the effect of limited number of operating frequencies on the performance of voltage-scaling algorithms. The optimal frequency grid which minimizes the effect of discrete operating frequencies is also derived. We then propose four alternative voltage-scaling schemes, Sys-Clock, PM-Clock, Opt-Clock and DPM-Clock. Each scheme is suitable for different hardware configuration which may have high or low voltage-scaling overhead and different taskset characteristics. We have implemented our voltage-scaling schemes on CMU?s real-time OS, Linux/RK, on the 3700 series Compaq iPAQ and a 733MHz XScale BRH board modified to support voltage-scaling.