Due to the increasing complexity of electronic systems the controllability and observability of advanced on-chip systems are getting more and more important. The functional density which is measured as the amount of functionality related to port width for outer access is permanently growing. Therefore tasks like manufacturing tests and functional debugging are becoming more difficult. In this work we present a synthesizable model for an integrated test and debugging unit which implements a Build-in Self Test (BIST) and an advanced debugging unit. In the debugging unit the scan-chain from testing is reused to get access to internal registers. The whole unit is designed as a wrapper to System-on-Chip (SoC) cores. To assess the usability of this approach the wrapper together with a processor core is prototyped and the functionality of the testing and debugging unit is demonstrated.