With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more architecture design points to reach a final optimum design. This exploration is currently performed using cycle accurate simulators that are accurate but slow, limiting a comprehensive search of design options. The vast design space and time to market economic pressures motivate the need for faster architectural evaluation methods.

The model presented in this paper facilitates a rapid exploration of the architecture design space for superscalar processors. It supplements current design tools by narrowing a large design space quickly, after which existing cycle accurate simulators can arrive at a precise optimum design. This allows a designer to select the final architecture design much faster than with traditional tools. The model calculates the instruction throughput of superscalar processors using a set of key architecture and application properties. It was validated with the Simplescalar out-of-order simulator. Results were within 5.5% accuracy of the cycle accurate simulator, but executed 40,000 times faster.