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13th IEEE International Workshop on Rapid System Prototyping (RSP'02)
RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs
Darmstadt, Germany
July 01-July 03
ISBN: 0-7695-1703-X
ASCII Text
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Natalino Busá, Ghiath Alkadi, Michael Verberne, Rafael Peset Llopis, Sethuraman Ramanathan, "RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs," Rapid System Prototyping, IEEE International Workshop on, pp. 159, 13th IEEE International Workshop on Rapid System Prototyping (RSP'02), 2002.
 
 
BibTex
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@article{ 10.1109/IWRSP.2002.1029752,
author = {Natalino Busá and Ghiath Alkadi and Michael Verberne and Rafael Peset Llopis and Sethuraman Ramanathan},
title = {RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs},
journal ={Rapid System Prototyping, IEEE International Workshop on},
volume = {0},
year = {2002},
issn = {1074-6005},
pages = {159},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWRSP.2002.1029752},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Rapid System Prototyping, IEEE International Workshop on
TI - RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs
SN - 1074-6005
SP
EP
A1 - Natalino Busá,
A1 - Ghiath Alkadi,
A1 - Michael Verberne,
A1 - Rafael Peset Llopis,
A1 - Sethuraman Ramanathan,
PY - 2002
KW - null
VL - 0
JA - Rapid System Prototyping, IEEE International Workshop on
ER -
 
Natalino Busá, Philips Research Laboratories
Ghiath Alkadi, Philips Research Laboratories
Michael Verberne, Philips Semiconductors B.V.
Rafael Peset Llopis, Philips Research Laboratories
Sethuraman Ramanathan, Philips Research Laboratories
Modern System-on-Chip (SoC) designs are steadily increasing in complexity, while verification strategies, based on traditional logic simulations, are becoming extraordinarily and intolerably slow. On the other side, Rapid System Prototyping frameworks are not yet scalable and modular enough to prototype complex multi-processor systems. The proposed solution offers a modular approach for the validation of SoCs containing up to 128 heterogeneous processors. The RSP framework is based on a multi-board PCI architecture. An inter-task, layered data synchronization protocol has been implemented in order to ease HW-SW partitioning, co-design and design space exploration.
Citation:
Natalino Busá, Ghiath Alkadi, Michael Verberne, Rafael Peset Llopis, Sethuraman Ramanathan, "RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs," rsp, pp.159, 13th IEEE International Workshop on Rapid System Prototyping (RSP'02), 2002
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