Efficient design method of configurable processors with complex instructions is described in this paper. In the proposed method, HDL descriptions of a RISC type processor are generated from two kinds of descriptions: the declaration of hardware components used in the design and a behavioral description of instructions at micro architectural level. This method has been implemented in an ASIP (Application Specific Instruction set Processor) development system PEAS-III. Using PEAS-III, application specific CISC can be designed easily. The results of case studies show that application specific CISC can be superior to RISC in terms of code size and execution cycles. In addition, the time for implementing CISC instructions can be drastically reduced compared with conventional design methods.