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Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01)
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications
Seoul, Korea
December 17-December 19
ISBN: 0-7695-1414-6
In this paper, we evaluate a low-cost fault-tolerance mechanism for microprocessors, which can detect and recover from transient faults, using multimedia applications. There are two driving force to study fault-tolerance techniques for microprocessors. One is deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is increasing popularity of mobile platforms. Recently cell phones are used for applications which are critical to our financial security, such as flight ticket reservation, mobile banking, and mobile trading. In such applications, it is expected that computer systems will always work correctly. From these observations, we have proposed a mechanism which is based on instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy. Unfortunately, we found significant performance loss when we evaluated the proposal using SPEC2000 benchmark suit. In this paper, we evaluate it using Media Bench which contains more practical mobile applications than SPEC2000.
Citation:
Toshinori Sato, Itsujiro Arita, "Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications," prdc, pp.225, Eighth Pacific Rim International Symposium on Dependable Computing (PRDC'01), 2001
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