In this paper, the memory columns (rows), include the redundancies, are partitioned into column blocks (row blocks), respectively. If the replacement is performed at the row-block level, then a row block-based FTM (RBFTM) system is used. Alternately, if the replacement is performed at the column-block level, then a column block-based FTM (CBFTM) system is used. If both approaches are incorporated into a memory chip, then the hybrid FTM (HFTM) system is achieved. Experimental results and analysis show that our fault-tolerant architectures can improve the yield for memory fabrication significantly. The reconfiguration mechanism requires almost negligible hardware overhead for high capacity memories. Moreover, the repair rates among different fault-tolerant strategies are also compared.