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Seventh Pacific Rim International Symposium on Dependable Computing (PRDC'00)
A reconfigurable fault-tolerant hypercube architecture with global sparing
Los Angeles, California
December 18-December 20
ISBN: 0-7695-0975-4
ASCII Text
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Siu-Cheung Chau, Ada Wai-Chee Fu, "A reconfigurable fault-tolerant hypercube architecture with global sparing," Pacific Rim International Symposium on Dependable Computing, IEEE, pp. 156, Seventh Pacific Rim International Symposium on Dependable Computing (PRDC'00), 2000.
 
 
BibTex
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@article{ 10.1109/PRDC.2000.897298,
author = {Siu-Cheung Chau and Ada Wai-Chee Fu},
title = {A reconfigurable fault-tolerant hypercube architecture with global sparing},
journal ={Pacific Rim International Symposium on Dependable Computing, IEEE},
volume = {0},
year = {2000},
isbn = {0-7695-0975-4},
pages = {156},
doi = {http://doi.ieeecomputersociety.org/10.1109/PRDC.2000.897298},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Pacific Rim International Symposium on Dependable Computing, IEEE
TI - A reconfigurable fault-tolerant hypercube architecture with global sparing
SN - 0-7695-0975-4
SP
EP
A1 - Siu-Cheung Chau,
A1 - Ada Wai-Chee Fu,
PY - 2000
KW - switching networks; fault tolerant computing; hypercube networks; reconfigurable architectures; reconfigurable fault-tolerant hypercube architecture; global sparing; switching networks; reliability
VL - 0
JA - Pacific Rim International Symposium on Dependable Computing, IEEE
ER -
 
Siu-Cheung Chau, Dept. of Phys. & Comput., Wilfrid Laurier Univ., Waterloo, Ont., Canada
Ada Wai-Chee Fu, Dept. of Phys. & Comput., Wilfrid Laurier Univ., Waterloo, Ont., Canada
We propose a new n-dimensional fault-tolerant hypercube architecture. We use (n-1) switching networks to connect the N=2/sup n/ active processors and k spare processors to form an n-dimensional fault-tolerant hypercube. The k spare processors can be used to back-up any k processor failures in the fault-tolerant hypercube. We call such a method global sparing and it is optimal in terms of the number of processor failures that can be back-up by k spare processors. The new architecture can achieve a higher level of reliability using less hardware compared to previously proposed schemes.
Index Terms:
switching networks; fault tolerant computing; hypercube networks; reconfigurable architectures; reconfigurable fault-tolerant hypercube architecture; global sparing; switching networks; reliability
Citation:
Siu-Cheung Chau, Ada Wai-Chee Fu, "A reconfigurable fault-tolerant hypercube architecture with global sparing," prdc, pp.156, Seventh Pacific Rim International Symposium on Dependable Computing (PRDC'00), 2000
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