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International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)
Communication Analysis for Network-on-Chip Design
Dresden, Germany
September 07-September 10
ISBN: 0-7695-2080-4
ASCII Text
x 
 
A. Siebenborn, O. Bringmann, W. Rosenstiel, "Communication Analysis for Network-on-Chip Design," Parallel Computing in Electrical Engineering, International Conference on, pp. 315-320, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.
 
 
BibTex
x
 
@article{ 10.1109/PCEE.2004.19,
author = {A. Siebenborn and O. Bringmann and W. Rosenstiel},
title = {Communication Analysis for Network-on-Chip Design},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2004},
isbn = {0-7695-2080-4},
pages = {315-320},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.19},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Communication Analysis for Network-on-Chip Design
SN - 0-7695-2080-4
SP315
EP320
A1 - A. Siebenborn,
A1 - O. Bringmann,
A1 - W. Rosenstiel,
PY - 2004
KW - null
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
A. Siebenborn, FZI Forschungszentrum Informatik, Germany
O. Bringmann, FZI Forschungszentrum Informatik, Germany
W. Rosenstiel, Universit?t T?bingen, Germany
In this paper we present an approach for the analysis of systems of parallel communicating processes, with regard to Network-on-Chip applications. We present a method to detect communications that synchronize the program flow of two or more processes. These synchronization points set the processes into relation and allow the determination of the global timing behavior of such a system. Using the results of our method for communication analysis, we present a new method to detect communications that might produce conflicts on shared communication resources. This information can be used to determine static routing in a packet routing network.
Citation:
A. Siebenborn, O. Bringmann, W. Rosenstiel, "Communication Analysis for Network-on-Chip Design," parelec, pp.315-320, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004
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