Compiler Scheduling for STA-Processors

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	Similar Articles Articles by Gordon Cichon Articles by P. Robelly Articles by H. Seidel Articles by M. Bronzel Articles by Gerhard Fettweis

International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04)

Dresden, Germany

September 07-September 10

ISBN: 0-7695-2080-4

	ASCII Text	x
	Gordon Cichon, P. Robelly, H. Seidel, M. Bronzel, Gerhard Fettweis, "Compiler Scheduling for STA-Processors," Parallel Computing in Electrical Engineering, International Conference on, pp. 45-60, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004.

	BibTex	x
	@article{ 10.1109/PCEE.2004.20, author = {Gordon Cichon and P. Robelly and H. Seidel and M. Bronzel and Gerhard Fettweis}, title = {Compiler Scheduling for STA-Processors}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2004}, isbn = {0-7695-2080-4}, pages = {45-60}, doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.20}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - Compiler Scheduling for STA-Processors SN - 0-7695-2080-4 SP45 EP60 A1 - Gordon Cichon, A1 - P. Robelly, A1 - H. Seidel, A1 - M. Bronzel, A1 - Gerhard Fettweis, PY - 2004 KW - null VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Gordon Cichon, Technische Universit?t, Dresden

P. Robelly, Technische Universit?t, Dresden

H. Seidel, Technische Universit?t, Dresden

M. Bronzel, Technische Universit?t, Dresden

Gerhard Fettweis, Technische Universit?t, Dresden

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2004.20

This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.

Citation:

Gordon Cichon, P. Robelly, H. Seidel, M. Bronzel, Gerhard Fettweis, "Compiler Scheduling for STA-Processors," parelec, pp.45-60, International Conference on Parallel Computing in Electrical Engineering, (PARELEC'04), 2004

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