International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)
Experimental Checking of Fault Susceptibility in a Parallel Algorithm
Warsaw, Poland
September 22-September 25
ISBN: 0-7695-1730-7
The paper deals with the problem of analyzing fault susceptibility of a parallel algorithm designed for a multiprocessor array (MIMD structure). This algorithm realizes quite complex communication protocol in the system. We present an original methodology of the analysis based on the use of software implemented fault injector. The considered algorithm is modeled as a multithreaded application. The experiment set up and results are presented and commented. The performed experiments proved relatively high natural robustness of the analyzed algorithm and showed further possibilities of its improvement.
Index Terms:
parallel algorithm, fault injection, multithreaded application, processor array
Citation:
Anna Derezińska, Janusz Sosnowski, "Experimental Checking of Fault Susceptibility in a Parallel Algorithm," parelec, pp.33, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002