loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
International Conference on Parallel Computing in Electrical Engineering (PARELEC'02)
Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform
Warsaw, Poland
September 22-September 25
ISBN: 0-7695-1730-7
ASCII Text
x 
 
Fayez Chayab, Lev Kirischian, Lucas Szajek, "Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform," Parallel Computing in Electrical Engineering, International Conference on, pp. 27, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002.
 
 
BibTex
x
 
@article{ 10.1109/PCEE.2002.1115192,
author = {Fayez Chayab and Lev Kirischian and Lucas Szajek},
title = {Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform},
journal ={Parallel Computing in Electrical Engineering, International Conference on},
volume = {0},
year = {2002},
isbn = {0-7695-1730-7},
pages = {27},
doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2002.1115192},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Parallel Computing in Electrical Engineering, International Conference on
TI - Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform
SN - 0-7695-1730-7
SP
EP
A1 - Fayez Chayab,
A1 - Lev Kirischian,
A1 - Lucas Szajek,
PY - 2002
KW - Parallel architecture
KW - partial reconfiguration
KW - FPGA
KW - automated synthesis
KW - data-flow applications
KW - DFG
KW - optimization
VL - 0
JA - Parallel Computing in Electrical Engineering, International Conference on
ER -
 
Fayez Chayab, RYERSON Polytechnic University
Lev Kirischian, RYERSON Polytechnic University
Lucas Szajek, RYERSON Polytechnic University
This paper presents an approach of automated architecture synthesis for a wide class of parallel multi-mode data-flow embedded computing systems. This approach is based on the method of automated synthesis of multi-mode architectures. This method allows finding the best correspondence between a multi-mode data-flow application (task) and its parallel processing architecture. This method has been implemented in an Architecture-to-Task Optimization System (ATOS) based on a Partially Reconfigurable Computing Platform (PRCP). It was estimated that ATOS could synthesize a complete architecture for an application presented in the form of a Data-Flow Graph within a few seconds including emulation and performance measurements on the PRCP. The proposed approach can dramatically decrease the cost of the R&D design stage and time-to-market for a wide range of parallel multi-mode embedded computing systems.
Index Terms:
Parallel architecture, partial reconfiguration, FPGA, automated synthesis, data-flow applications, DFG, optimization
Citation:
Fayez Chayab, Lev Kirischian, Lucas Szajek, "Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform," parelec, pp.27, International Conference on Parallel Computing in Electrical Engineering (PARELEC'02), 2002
Usage of this product signifies your acceptance of the Terms of Use.