Automatic Design of VLSI Pipelined LMS Architectures

P
PARELEC
2000
International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)
Abstract - Automatic Design of VLSI Pipelined LMS Architectures

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International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)

Quebec, Canada

August 27-August 30

ISBN: 0-7695-0759-X

	ASCII Text	x
	Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Daniel Massicotte, "Automatic Design of VLSI Pipelined LMS Architectures," Parallel Computing in Electrical Engineering, International Conference on, pp. 144, International Conference on Parallel Computing in Electrical Engineering (PARELEC'00), 2000.

	BibTex	x
	@article{ 10.1109/PCEE.2000.873618, author = {Anne-Claire Guillou and Patrice Quinton and Tanguy Risset and Daniel Massicotte}, title = {Automatic Design of VLSI Pipelined LMS Architectures}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2000}, isbn = {0-7695-0759-X}, pages = {144}, doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2000.873618}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - Automatic Design of VLSI Pipelined LMS Architectures SN - 0-7695-0759-X SP EP A1 - Anne-Claire Guillou, A1 - Patrice Quinton, A1 - Tanguy Risset, A1 - Daniel Massicotte, PY - 2000 VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Anne-Claire Guillou, IRISA

Patrice Quinton, IRISA

Tanguy Risset, IRISA

Daniel Massicotte, Universit? du Qu?bec ? Trois Rivi?res

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2000.873618

We present the use of MMAlpha, a tool for the design of parallel VLSI architectures, for the automatic generation of pipelined LMS adaptive filters. Starting from the equations of the applications, MMAlpha allows one to derive a VHDL description of architecture at the register transfer level. We describe the design flow of MMAlpha, which goes through uniform, scheduling, mapping and hardware generation. Results obtained for implementing a delayed LMS algorithm and a look-ahead delayed LMS algorithm on a FPGA Virtex XCV800 chip are shown.

Citation:

Anne-Claire Guillou, Patrice Quinton, Tanguy Risset, Daniel Massicotte, "Automatic Design of VLSI Pipelined LMS Architectures," parelec, pp.144, International Conference on Parallel Computing in Electrical Engineering (PARELEC'00), 2000

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