We present the use of MMAlpha, a tool for the design of parallel VLSI architectures, for the automatic generation of pipelined LMS adaptive filters. Starting from the equations of the applications, MMAlpha allows one to derive a VHDL description of architecture at the register transfer level. We describe the design flow of MMAlpha, which goes through uniform, scheduling, mapping and hardware generation. Results obtained for implementing a delayed LMS algorithm and a look-ahead delayed LMS algorithm on a FPGA Virtex XCV800 chip are shown.