Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System

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International Conference on Parallel Computing in Electrical Engineering (PARELEC'00)

Quebec, Canada

August 27-August 30

ISBN: 0-7695-0759-X

	ASCII Text	x
	Lev Kirischian, "Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System," Parallel Computing in Electrical Engineering, International Conference on, pp. 100, International Conference on Parallel Computing in Electrical Engineering (PARELEC'00), 2000.

	BibTex	x
	@article{ 10.1109/PCEE.2000.873610, author = {Lev Kirischian}, title = {Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System}, journal ={Parallel Computing in Electrical Engineering, International Conference on}, volume = {0}, year = {2000}, isbn = {0-7695-0759-X}, pages = {100}, doi = {http://doi.ieeecomputersociety.org/10.1109/PCEE.2000.873610}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Parallel Computing in Electrical Engineering, International Conference on TI - Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System SN - 0-7695-0759-X SP EP A1 - Lev Kirischian, PY - 2000 KW - Reconfigurable architecture: FPGA KW - Architecture selection graph KW - Graph arrangement VL - 0 JA - Parallel Computing in Electrical Engineering, International Conference on ER -

Lev Kirischian, Ryerson Polytechnic University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PCEE.2000.873610

This paper presents the architecture organization of a task adaptive reconfigurable high-performance computing system for parallel processing of data-flow tasks, The architecture of this reconfigurable system allows flexible distribution of uniform configurable resources (FPGA-based) between tasks, Each task corresponds to a specific Group Processor (GP) adapted for the task requirements. The paper discusses the method of selecting the optimal group processor configuration and mapping group processors on the field of configurable resources. The performance results of the first prototype of the ARGO-parallel computing system are presented.

Index Terms:

Reconfigurable architecture: FPGA, Architecture selection graph, Graph arrangement

Citation:

Lev Kirischian, "Optimization of Parallel Task Execution on the Adaptive Reconfigurable Group Organized Computing System," parelec, pp.100, International Conference on Parallel Computing in Electrical Engineering (PARELEC'00), 2000

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