Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes

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	Similar Articles Articles by Zaid Al-Ars Articles by Ad J. van de Goor

2003 International Workshop on Memory Technology, Design and Testing (MTDT'03)

San Jose, California

July 28-July 29

ISBN: 0-7695-2004-9

	ASCII Text	x
	Zaid Al-Ars, Ad J. van de Goor, "Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes," Memory Technology, Design and Testin, IEEE International Workshop on, pp. 27, 2003 International Workshop on Memory Technology, Design and Testing (MTDT'03), 2003.

	BibTex	x
	@article{ 10.1109/MTDT.2003.1222357, author = {Zaid Al-Ars and Ad J. van de Goor}, title = {Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes}, journal ={Memory Technology, Design and Testin, IEEE International Workshop on}, volume = {0}, year = {2003}, issn = {1087-4852}, pages = {27}, doi = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2003.1222357}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Memory Technology, Design and Testin, IEEE International Workshop on TI - Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes SN - 1087-4852 SP EP A1 - Zaid Al-Ars, A1 - Ad J. van de Goor, PY - 2003 KW - DRAMs KW - dynamic faults KW - two floating nodes KW - defect simulation KW - memory testing VL - 0 JA - Memory Technology, Design and Testin, IEEE International Workshop on ER -

Zaid Al-Ars, Delft University of Technology

Ad J. van de Goor, Delft University of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MTDT.2003.1222357

The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a new analysis method to apply electrical simulation for investigating the faulty behavior resulting from defects causing two floating nodes within the memory. The paper also presents the results of a simulation study performed on bit line opens to validate the newly proposed method, and suggests a test to detect these bit line opens.

Index Terms:

DRAMs, dynamic faults, two floating nodes, defect simulation, memory testing

Citation:

Zaid Al-Ars, Ad J. van de Goor, "Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes," mtdt, pp.27, 2003 International Workshop on Memory Technology, Design and Testing (MTDT'03), 2003

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